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Altera_Forum
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10 years ago

How to use FPGA delay one signal edge in 1 ns while keep other edge unchange?

Hi, Recently I am thinking is it possible to use a FPGA device do such kind of thing: Use FPGA generate USART mater transmit signals, a 30Mhz clock, each clock cycle generate a bit data. ...
Altera_Forum's avatar
Altera_Forum
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10 years ago

As I look at the SV device datasheet, the fastest clock tree speed is ~700MHz only which is lower than the 800 MHz. Note that this is the max specs and generally it would be difficult to achieve it. Considering timing closure issue, I think normally the core speed achievable would be much lower as Tricky mentioned.