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Altera_Forum
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10 years ago

How to use FPGA delay one signal edge in 1 ns while keep other edge unchange?

Hi, Recently I am thinking is it possible to use a FPGA device do such kind of thing: Use FPGA generate USART mater transmit signals, a 30Mhz clock, each clock cycle generate a bit data. ...
Altera_Forum's avatar
Altera_Forum
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10 years ago

This is sometimes done by making the wire for the clock slightly longer than the wire for the data. This could also be applied to traces on a PCB. Using the constraint Tricky mentioned above works by adding cells for the purpose of delaying the signal.