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Honored Contributor
Honored ContributorHow to use FPGA delay one signal edge in 1 ns while keep other edge unchange?
Hi, Recently I am thinking is it possible to use a FPGA device do such kind of thing: Use FPGA generate USART mater transmit signals, a 30Mhz clock, each clock cycle generate a bit data. ...
Altera_ForumHonored Contributor
Honored ContributorI want to change a little bit each time when I transmit data out, so constraint in sdc doesn't work for this.
