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Altera_Forum
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10 years ago

How to use FPGA delay one signal edge in 1 ns while keep other edge unchange?

Hi, Recently I am thinking is it possible to use a FPGA device do such kind of thing: Use FPGA generate USART mater transmit signals, a 30Mhz clock, each clock cycle generate a bit data. ...
Altera_Forum's avatar
Altera_Forum
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10 years ago

800mhz clock is far to fast for an FPGA.

But what you want to do is more an IO pin delay spec. You cannot garantee specific delays inside an FPGA.

You need to use the set_output_delay sdc constraint in your .sdc file.