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Joakim's avatar
Joakim
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

How to use D5_DELAY or D5_OE_DELAY on Cyclone V

I'm desperately trying to get the timing to work between my Cyclone V and an external CPU. Because of the clock delay, it seem to be impossible to get the timing to pass within one clock cycle, so I ...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii53024.pdf

Page 7-6 Input/Output Constraint

Page 7-9 Creating Multicycle Exceptions

By default, the TimeQuest analyzer performs a single-cycle analysis to determine the setup and hold checks. Also, by default, the TimeQuest Timing Analyzer sets the end multicycle setup assignment value to one and the end multicycle hold assignment value to zero.

You may refer to Page 7-14 for the examples of applying multicycle for different conditions. You have to examine which condition fit your design requirement.

If you use multicycle paths that cross different clock domains, you must carefully examine the timing paths in the TimeQuest analyzer before and after applying the multicycle exception to determine if the launch and latch clock edges function as you intend.

Thanks.