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Altera_Forum
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13 years ago

How to synchronize a PLL with a clock signal

In my design I require there to be a 100 mhz clock signal and a 50 mhz clock signal. I have an 50 mhz clock source so I decided to use a PLL to convert it to a 100 mhz clock. The only issue I have is...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Bring the 50 MHz clock into the PLL, and then create two output clocks; one at 50 MHz and the other at 100 MHz. Don't use the input 50 MHz for anything except to feed the PLL. Use the 50 MHz output from the PLL inside your design. The 50 and 100 MHz clocks from the PLL will then be phase aligned to their rising edges by design, guaranteed every time out of reset. It will always look like your top timing diagram, not the bottom one. This is independent of feedback mode.