Honored Contributor
Honored ContributorThx for all the answer.
@agdeput: i can understand and that could be a big problem almost for all, but I hope that with a bit more investigation it's possible to bypass the problem (I'm thinking about strictly post fit or at least post fit netlist should resolve the problem, if the signal tap still fit in the design with that constraint) @alias: in my design I'm planning 4 big partition and 1 is all the SOPC modules (nios and peripheral) - the aim is that the 3 people that work at the design can work on their part and then I'll import their netlist in the top. Thanks for the feedback it's important to know that. What about my approach? Shall be ok? At the moment I've done the 4 "macropartition at the top" and generated the TCL in order to create the sub design: today I'll try to generate the netlist, estimate the dimension of the partition (# of logic elements, ram, dsp block, etc..) and then at the end I'll import all in the top (and I'll pray to understand more..) I still have some approach problem, I mean in which partition keep the clock management blocks? I mean shall I keep that in the partition of design where they're used more? Keep all the PLL and clk generating block on the top (in no partition)? To me seems the better way, but I'm not sure about it: at the moment in my partition division I've keep on the top only the PLL and clk that I wanna be global signal, whereas all the regional ones still be on their partitions. Thx a lot for the answers, I'm happy to not be alone in this experimentation.
