How to set waitrequestAllowance to 1 for an Arria 10 EMIF core

Alright, I get what you are trying to do now.

However since this is internal setting hardcoded in EMIF IP, we both aligned that we don't want to mess with it to prevent breaking the EMIF IP functionality.

Even if you manage to optimize the data transfer on Avalon bus but if memory controller is not ready to process the data then it won't help much in overall BW or throughput performance.

Therefore, as alternate option, feel free to checkout EMIF user guide doc (chapter 13) for some tips in optimizing memory controller.

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf

Thanks.

Regards,

dlim