How to set waitrequestAllowance to 1 for an Arria 10 EMIF core

I am trying to optimize the performance of the interface driving the slave interface of the DDR4 controller. Per the Avalon Interface Specification:

waitrequestAllowance:

Specifies the number of transfers that can be issued or

accepted after waitrequest is asserted.

When the waitrequestAllowance is 0, the write,

read and waitrequest signals maintain their existing

behavior as described in the Avalon-MM Signal Roles

table.

When the waitrequestAllowance is greater than 0,

every clock cycle on which write or read is asserted

counts as a command transfer. Once waitrequest is

asserted, only waitrequestAllowance more

command transfers are legal while waitrequest

remains asserted. After the waitrequestAllowance

is reached, write and read must remain deasserted

for as long as waitrequest is asserted.

Once waitrequestdeasserts, transfers may resume

at any time without restrictions until waitrequest

asserts again. At this time, waitrequestAllowance

more transfers may complete while waitrequest

remains asserted.

A waitrequestAllowance of greater than 0 (I am hoping for a value of 1) allows the master to send one more word of data after waitrequest is asserted by the slave (i.e. the EMIF). With a waitrequestAllowance of 1 I get an extra clock to decide on backing off, which allows registering control signals thus eliminating some asynchronous delays.