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Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

How to set waitrequestAllowance to 1 for an Arria 10 EMIF core

I would like to use a waitrequestAllowance of 1 with a DDR4 EMIF core in an Arria 10 design. This parameter appears in the .sopcinfo file (which I don't want to mess with, for obvious reasons), but ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

You have the right mindset where user shouldn't mess around with DDR4 IP internal setting.

waitrequestAllowance looks exactly like one of these internal setting that shouldn't be touched by user.

  • So, may I know why would you want to control it ?
  • Or can you explain further what are you trying to do with DDR4 IP here ?
  • Ideally user should only control the interface signal exposed on DDR4 IP top level design only

If I look at the EMIF user guide doc, the closest user controlled signal should be "amm_ready" signal that indicate whether DDR4 memory controller is busy or not.

  • amm_ready is the inverse of amm_wait_request signal
  • User should only send command request to DDR4 memory controller whenever it's ready to accept command when amm_ready assert high

Thanks.

Regards,

dlim