Occasional Contributor
Occasional ContributorThanks for your patience! I think I am close to the answer now.
> for input, external device has their own clock, so we need to use virtual clock for timing constraint.
> for output, for example, FPGA as SPI master to external device. The clock is provided by fpga, so there is no need to use virtual clock.
> for output, for example, FPGA as SPI slave to external device. The clock is provided by external device, so we need to use virtual clock.
> for uart communication, it's asynchronous communication, there is no clock. So we don't need to set any timing contraints.
Please check if my above understanding is right or not. Thanks!
Super ContributorYou never need to not create timing constraints. For asynchronous interfaces, you'd probably be using false path exceptions.
