how to set timing constraints for source synchronous inputs

Synchronous I/O means that an external clock source (or 2 separate sources sometimes) are used to drive both the source and destination device. Source synchronous means there is a clock that drives the source device and then the source device provides the clock to the destination device to latch the data.

I think you're also misunderstanding the meaning of a virtual clock. A virtual clock is still a real clock. It's just that it never actual enters the FPGA. Even though it never enters the FPGA, timing constraints (create_clock with no target specified) still need to describe its properties. Then, a create_clock command (with a target specified, usually the clock input port of the device) defines the relationship between the clock that actually enters the FPGA and the virtual clock. Having set_input_delay reference the virtual clock establishes the launch edge for an input analysis. The tool knows what clock domain drives the input latching registers of the FPGA so the latch edge is determined automatically simply by having set_input_delay target particular inputs.

As for bidirectional interfaces, you would have set_input_delay and set_output_delay constraints applied to the same I/O.