how to set timing constraints for source synchronous inputs

(1) What's the difference of source synchronous outputs and regular synchronous outputs?

For example, SPI bus, so this is source synchronous outputs, no need virtual clock.

Uart, there is no register clock output, need use virtual clock.

Is my understanding right?

"But how does fpga know the relationship between virtual clock and actual input clock & output clock?"

I mean physically, all the timing constraints should refer to real clock. So if we define input timing constraint based on virtual clock,

we need to define the relationship between virtual clock and real input clock. if not defined, how can fpga knows which input pin & register should meet such timing constraints? So I am confused with set_input_delay based on virtual clock, not based on real input clock.