how to set timing constraints for source synchronous inputs

(1) Again, as I said, for source synchronous outputs, there is no virtual clock. For regular synchronous outputs, yes there is a virtual clock, the clock that drives the "downstream" device. But since you're talking about source synchronous outputs, there is no virtual clock.

"But how does fpga know the relationship between virtual clock and actual input clock & output clock?"

I don't understand this question unless you separate into inputs and outputs. For source synchronous inputs, the virtual clock is the launch clock and the clock that drives the input registers (either direct clocking from upstream device or clock processed through a PLL) is the latch clock. You define this clock relative to the virtual clock (same edge or opposite edge requiring a phase shift). For source synchronous outputs, the launch clock is the clock that drives the output registers and the latch clock is the output generated clock.

(4) No idea what's happening here. All I can say is that from the error message, something is happening with read_cnt[2] somewhere where the tool is seeing it as a clock. Make sure you're not accidentally using this signal elsewhere in your design. You can also search the RTL Viewer to see if you can see where read_cnt[2] is going into the clock input of some logic somewhere.