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BXia
Occasional Contributor
Occasional ContributorHow to set the LVDS SERDES intel FPGA IP for receiving mini-LVDS signal
Hi,
I'm using the LVDS SERDES intel FPGA IP to receive Mini-LVDS signal, I need to receive 2 data by a clock, however, the minimum SERDES factor is 3, so how to set the IP, or anything else I need ...
JohnT_Altera
Regular Contributor
Regular ContributorHi,
It will depend on the speed grade of the device use and also whether you are able to close the timing in Timing Analyzer
