Forum Discussion

BXia's avatar
BXia
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

How to set the LVDS SERDES intel FPGA IP for receiving mini-LVDS signal

Hi, I'm using the LVDS SERDES intel FPGA IP to receive Mini-LVDS signal, I need to receive 2 data by a clock, however, the minimum SERDES factor is 3, so how to set the IP, or anything else I need ...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


If you are using x2 factor than you cannot use the LVDS Deserializer as it only support x3-x10. To support SDR and DDR then you will need to use Intel GPIO IP.


Below is the note from the Device LVDS userguide.


The IOE contains two data input registers that can operate in DDR or SDR mode. You can bypass the deserializer to support DDR (x2) and SDR (x1) operations. The deserializer bypass is supported through the GPIO IP core.