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RLee42
Occasional Contributor
Occasional ContributorHow to set SDC constraints for cross clock sample?
My device is Cyclone III EP3C16F256. In my design, I have two clock, clk2 is derived from clk1 in PLL with 180 degree phase shift. There is 1bit data in clk2 clock domain which need to be sampled in...
sstrell
Super Contributor
Super ContributorThe clock domains are synchronous to each other, so you can use multicycle timing exceptions to choose the correct edges for setup and hold analysis.
While you're not creating an external source synchronous interface, it sounds like you're creating something similar internally. See the timing exceptions section of this OLT for ideas on the multicycle exceptions you'll need:
https://www.intel.com/content/www/us/en/programmable/support/training/course/ocss1000.html
