How to set SDC constraints for cross clock sample?

The clock domains are synchronous to each other, so you can use multicycle timing exceptions to choose the correct edges for setup and hold analysis.

While you're not creating an external source synchronous interface, it sounds like you're creating something similar internally. See the timing exceptions section of this OLT for ideas on the multicycle exceptions you'll need:

https://www.intel.com/content/www/us/en/programmable/support/training/course/ocss1000.html