Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

How to set analog delay MaxPlusII

Hi, I need to set a delay following a rising_edge of a sig_a. In order to do that, I have utilized the: c<=sig_a; x <= c after# nS; -- where I can select the# through a data on the bus. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I found, that keep synthesis attribute is ignored with EPM7000 devices (and probably other simple CPLD). I had tried with MAX II before, which works O.K. There may be other techniques to achieve the intended behaviour with EPM7000, but I didn't use these devices since about 10 years and can't help in detail.