Forum Discussion
Altera_Forum
Honored Contributor
13 years agoOk for the advice!
Now I finally implemented my first MSI Interrupt. But 1 ) why I can not get pci-msi-edge on my device after the linux command:cat /proc/interrupts while it looks good with the command lspci -d 1204:ec30 -v -xxx ( see the 2 outputs below) 2) I permanently get an error by implementing pci_enable_msi_block (struct pci_dev * dev, unsigned int nvec) where can I get the related patch for arch x86?
# lspci -d 1204:ec30 -v -xxx
04:00.0 Non-VGA unclassified device: Lattice Semiconductor Corporation Device ec30
Subsystem: Lattice Semiconductor Corporation Device 3030
Physical Slot: 3
Flags: bus master, fast devsel, latency 0, IRQ 30
Memory at d0440000 (32-bit, non-prefetchable)
Memory at d0400000 (32-bit, non-prefetchable)
Capabilities: Power Management version 3
Capabilities: MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: Express Endpoint, MSI 00
Capabilities: Device Serial Number 00-00-00-00-00-00-00-00
00: 04 12 30 ec 07 04 10 00 00 00 00 00 10 00 00 00
10: 00 00 44 d0 00 00 40 d0 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 04 12 30 30
30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 70 03 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 05 90 81 00 0c 10 e0 fe 00 00 00 00 a9 41 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 10 00 01 00 00 80 00 00 00 00 00 00 11 74 00 00
a0: 00 00 11 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
# cat /proc/interrupts
CPU0
0: 116261 IO-APIC-edge timer
1: 2 IO-APIC-edge i8042
3: 2 IO-APIC-edge
4: 2 IO-APIC-edge
5: 0 IO-APIC-edge parport0
7: 0 IO-APIC-edge LATTICE_pci
8: 1 IO-APIC-edge rtc0
9: 0 IO-APIC-fasteoi acpi
12: 4 IO-APIC-edge i8042
16: 79998 IO-APIC-fasteoi pciehp, pciehp, pciehp, pciehp, ehci_hcd:usb2, ohci_hcd:usb6, ohci_hcd:usb7, ohci_hcd:usb8, HDA Intel
18: 0 IO-APIC-fasteoi mmc0, mmc1
19: 13861 IO-APIC-fasteoi ehci_hcd:usb1, ohci_hcd:usb3, ohci_hcd:usb4, ohci_hcd:usb5
24: 0 PCI-MSI-edge aerdrv
25: 2 PCI-MSI-edge aerdrv, pciehp
--- Quote Start --- Yes. If you have a single MSI vector, you have to register 1 interrupt line. If you want to test CAN, UART interrupts, than write your kernel module. Request irq for CAN, than for UART, with interrupt handlers. For ex: static irqreturn_t can_isr ( int irq, void *dev ) { void testCAN(); printk(KERN_DEBUG " CAN received irq = %d \n", irq); return IRQ_HANDLED; } static irqreturn_t uart_isr ( int irq, void *dev ) { void testUART(); printk(KERN_DEBUG " UART received irq = %d \n", irq); return IRQ_HANDLED; } --- Quote End ---