How to remove glitches on Incoming signals ?

So you are stuck with what signals you've got inside the chip.

There is no ready made solution. It depends on your signal. For some cases a pulse of 100ns is a glitch for others its a valid signal. What I suggest you to do is to look at the problem with digital designer glasses on and ask: "How can I design a digital state-machine which will distinguish a false signal from a valid signal". Imagine all the senarios which are likely to occour. You will probably end up finding that you will have to discriminate against pulse width, so you need a counter to hold track of time. Bottom line: you will be designing a state-machine to solve your problem. But be prepared to face a problem without a solution: if your glitch has same shape (time duration) as a valid signal and you have no further information about the signal such as relation to previous events, then there is no way to distinguish good from bad. Your only chance is if you can redesign the communication protocol, such that it is will detect errors, I.e. you must change the transmitter card as well. There are countles ways to make error resiliant channels.

In case you will be doing re-design of the interconnect, seriously consider using differential signaling. Chances are that much of your noise is due to common mode differences between your cards. Differential signaling makes life much simpler in that respect. Many Altera chips have LVDS ports.

Attached is a way to build a scmitt trigger input using an internal gate in the FPGA and a couple of resistors. I have not tried this myself in practice, only simulated, so do simulate and test before commiting.