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Thank you for your reply. You are right, Xilinx only do data in this scenario. We have a product using this feature from Xilinx right now, I don't know the details but Xilinx transceiver picks the sample point close to the middle automatically based on statistics.
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The Altera parts can probably be configured to do it automatically too. The eyeQ feature of the receiver allows you to control the sampling location for data rates up to 3.5Gbps, so you may want to consider using that to evaluate how well the receiver is selecting the center of the eye pattern.
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Do you mind point me to the Altera documentation you mentioned about using over-sampling to receive data?
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Search for over-sampling in the Stratix IV handbook. There is one mention of it under CPRI.
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Is the phase picking process automated on Altera side?
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It is in lock-to-data mode for regular data rates. I do not know what it does for over-sampled data rates.
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311.04Mbps 8B10B encoded bit stream
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You will not be able to use 8/10B decoding in the receiver hard IP. You will have to decode after you receive the oversampled data into the fabric.
Why not use the LVDS receivers at this data rate?
Cheers,
Dave
Honored Contributor
