--- Quote Start ---
Is there a way to use the GXB in Stratix IV to recover data/clock from a bit stream slower than 600Mbps? I know Xilinx transceivers can do this using oversampling.
--- Quote End ---
Do you have a reference for the Xilinx statement?
The Altera documentation also states that you can use over-sampling to receive data ... though it may only apply to
data. You need to be careful when reading marketing material :)
The CDR uses data transitions to generate a signal to lock the PLL to. I would be surprised if you could lock a CDR programmed to expect a data rate of 1Gbps with transitions only at 500Mbps or 250Mbps. However, if you keep the CDR in lock-to-reference mode, and both the transmitter and receiver use a common reference, then you could use the eyeQ feature to get the receiver in the center of the eye, and use logic at the output to check that each over-sampled sample has the same value, eg. pairs of oversampled-by-2 have the same value.
You'll have to perform some hardware tests to see if you can see what works and what does not.
Cheers,
Dave
Honored Contributor
