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hans86
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6 years ago

How to program an ALTPLL_RECONFIG core?

Hi All, I using the ALTPLL_RECONFIG core on a CycloneIV and it seems to work fine except that I can't seem to duplicate the initial state mif file settings. When I simulate the core I get clk0=100M...
hans86's avatar
hans86
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6 years ago

Hi Anand,

Thanks for the follow up, I found the answer to my point 1, as described in the CycloneIV Device Handbook from 2016 it states:

Post-scale counter cascading is automatically set by the Quartus II software in the configuration file. Post-scale counter cascading cannot be performed using the PLL reconfiguration.

I was using the ALTPLL (Phase-Locked Loop) IP Core User Guide and the Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) IP Core User Guide both from 2017 neither mention this fact. It explains the C1 value of 625 which a user can't get to with an 8 bits register.

So the conclusion is that the values defined during Quartus IP configuration cannot all be reproduced using the ALTPLL_RECONFIG or with the mif file.

I think a warning during the ALTPLL configurations (when users click the dynamic configuration option and uses a too low frequency) would be very helpful.

Thanks for replying you did give me a good hint to investigate the mif file,

Thanks,

Hans.