how to program adxl345 on DE10-Lite in verilog?

hello all,

as the title, I'm trying to read the device ID of adxl345 on my board in 4-wire SPI, but I have some problems, I get the wrong device ID (every bit is one).

The following is my code, and I don't kwon where I make mistakes. Can anyone tell where I make mistakes and how to get the correct device ID?

module sensor(sw0,clk,hex0,sdo,sdi,cs,sclk);
input sw0,clk;
output  hex0;
input sdo;
output cs,sdi,sclk;
reg cs,next_cs;
reg sclk_ctrl,next_sclk;
reg sdi,next_sdi;
reg  address;
reg  data,next_data;
reg  cnt,next_cnt;
reg  state,next_state;
pll p0(
    .inclk0(clk),
    .c0(clk2)
    );
    
assign sclk=(sclk_ctrl)?clk2:1'b1;
assign hex0=(cs)?data:8'd255;
always @(negedge clk2) begin
    if(sw0) begin
        state<=next_state;
        cs<=next_cs;
        sclk_ctrl<=next_sclk;
        cnt<=next_cnt;
        sdi<=next_sdi;
        data<=next_data;
    end
    else begin
        state<=3'd0;
        cs<=1'b1;
        sclk_ctrl<=0;
        cnt<=4'd15;
        address<=8'b11000000;
        sdi<=1'b0;
        data<=8'd0;
    end
end
always @(*) begin
    case (state)
        3'd0:        begin //pull cs to 0
                        next_state=(sw0)?3'd2:3'd0;
                        next_cs=1'b0;
                        next_sclk=1'b0;
                        next_cnt=4'd15;
                        next_sdi=1'b0;
                        next_data=data;
                    end
        3'd2:        begin    //make sclk be a 1MHz clock and input register adrdess through sdi
                        next_state=(cnt==8)?3'd3:3'd2;
                        next_cs=1'b0;
                        next_sclk=1'b1;
                        next_cnt=cnt-8'd1;
                        next_sdi=address;
                        next_data=data;
                    end
        3'd3:        begin    //receive the output of sdo
                        next_state=(cnt==0)?3'd4:3'd3; 
                        next_cs=1'b0;
                        next_sclk=1'b1;
                        next_cnt=cnt-8'd1;
                        next_sdi=1'bx; 
                        next_data={data,sdo};                     
                    end
        3'd4:        begin //data transmission is completed,pull cs and sclk to 1
                        next_state= 3'd5; 
                        next_cs=1'b0;
                        next_sclk=1'b0;
                        next_cnt=cnt;
                        next_data=data; 
                    end
        3'd5:        begin
                        next_state=(sw0)?3'd5:3'd0; 
                        next_cs=1'b0;
                        next_sclk=1'b0;
                        next_cnt=cnt;
                        next_data=data; 
                    end
                    
        default:    begin
                        next_state=(sw0)?3'd1:3'd0;
                        next_cs=1'b1;
                        next_sclk=1'b0;
                        next_cnt=4'd15;
                        next_sdi=1'b0;
                        next_data=8'd0;
                    end
    endcase
end
endmodule 

and this is the result(using signal tap)

https://www.edaboard.com/attachment.php?attachmentid=145116&d=1520248193&thumb=1 (https://www.edaboard.com/attachment.php?attachmentid=145116&d=1520248302)

thanks