How to prevent the synthesizer from optimizing signals away? Fanout?
Using: 5M570 Max V CLPD speed grade 5. CLK_IN is and in port div_clk(3 downto 0) is a signal I have a clock that is derived from a counter to provide divide by 4 functionality, and other prescale...
After understanding how the vhdl code, you should be able to understand and write the coding in the way to limit the fan out. You can also cross probe the rtl viewer to look into the design where does the code refer to. This will speed your way on the coding side but you first need to understand how VHDL to be written.
That was the one little piece of information I was asking for originally. I added 2 separate signals to the vhdl after the initial prescaling counter :Mclk1 <= div_count[1]Mclk2 <= div_count[1]They are defined in the assignment editor to global clocks and are used in other processes. I think there is a do not optimize option as well but they still get optimized away. Is there an vhdl command in quartus that works something like "asm" in C?I'd edit them directly in the net list with a text editor or rtl viewer but I keep getting thwarted by the software. I'll have a look at the course. Thanks.
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