How to prevent the synthesizer from optimizing signals away? Fanout?

I did not think the MAX V had a PLL? I haven't played with the RTL view much. Although it seems far more intuitive. I take it the 12{1} means 12 of div_counter[1] into that logic block? Mark

Is there documentation on how to directly edit the RTL in Quartus II? I can get to the RTL viewer but can't make modificatoins there.

These two includes at the top worked. library altera; use altera.altera_syn_attributes.all; Along with the VHDL: attribute keep : boolean; attribute keep of MASTER_CLK : signal is true; attribute keep of MASTER_CLK1 : signal is true; This preserved the two clock signals. I had omitted the “library altera;” when trying this earlier. Increasing fmax and how: Varying which version of master clock each process received yielded a few MHz improvement in fmax. Greater improvement was realized by assigning logic to specific areas, aka floor planning. The devices assignment window and qsf file was used for this, but this only yielded an fmax of 21Mhz. The greatest benefit came from use of the Tools>Advisors>Timing optimization advisor. Timing Optimization Advisor: Setting “Placement Effort Multiplier” to 4 and, Setting “Fitting Initial Placement Seed” from 40-50 Achieved an fmax of 29Mhz, and a little bit more fiddling with which master clock each process used yeilded 31Mhz. I see you can use the Design Space Explorer to vary the seed starting point to optimize a design. I'll try that next. I've exceeded my fmax by a few MHz. Thank you for your help.