Forum Discussion
Altera_Forum
Honored Contributor
12 years ago --- Quote Start --- rd_addr : in integer range 0 to 255; kaz,why rd_addr is input ,why isn't output such as rd_data --- Quote End --- we are talking here about RAM (not CAM) so any address is always input. Data can be either input(wr_data) or output(rd_data). vout(valid out) is a signal I added to flag that output is ready. so far you have been developing this design but without clear spec as what are your given inputs and what is your output format. I assume it is practice but you really should start from clear spec.