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12 years agothanks kaz , y really helped me
first i tried to make vhdl code for dual port ram because i will compare between two samples ..is it right thing??? but i have a problem when i tray to test the test bench is (all generics must take a default value) here is code i need your help... library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bram_tdp is generic ( DATA : std_logic_vector (0 to 6) ; ADDR : std_logic_vector (0 to 6)); port ( -- Port A a_clk : in std_logic; a_wr : in std_logic; a_addr : in std_logic_vector(6 downto 0); a_din : in std_logic_vector(6 downto 0); a_dout : out std_logic_vector(6 downto 0); -- Port B b_clk : in std_logic; b_wr : in std_logic; b_addr : in std_logic_vector(6 downto 0); b_din : in std_logic_vector(6 downto 0); b_dout : out std_logic_vector(6 downto 0) ); end bram_tdp; architecture rtl of bram_tdp is -- Shared memory type mem_type is array ( 6 downto 0 ) of std_logic_vector(6 downto 0); shared variable mem : mem_type; begin -- Port A process(a_clk) begin if(a_clk'event and a_clk='1') then if(a_wr='1') then mem(conv_integer(a_addr)) := a_din; end if; a_dout <= mem(conv_integer(a_addr)); end if; end process; -- Port B process(b_clk) begin if(b_clk'event and b_clk='1') then if(b_wr='1') then mem(conv_integer(b_addr)) := b_din; end if; b_dout <= mem(conv_integer(b_addr)); end if; end process; end rtl;