New ContributorHow to manually run a gate-level simulation in quartus?
As you can see in this question's image I configured a VHDL project in quartus to automatically run gate-level simulation after compilation by going in Assignments->Settings and clicking "Automatically run gate-level simulations after compilation".
However, compilation takes time and on some already compiled projects I might want to re-run a simulation...
How do I simply re-run the simulation without needing to recompiling the whole project?
In the same context: if I change only me test file, do I need to recompile the whole project? Or am I able to only recompile the needed test file?
Hi
How do I simply re-run the simulation without needing to recompiling the whole project?
Make sure no changes to the test file and do not delete the simulation folder. If not, have to run the eda netlist writer again.
if I change only me test file, do I need to recompile the whole project? Or am I able to only recompile the needed test file?
Make sure your testbench file is not included under project navigator, then not need recompile the whole project.
