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Altera_Forum
Honored Contributor
Honored ContributorHow to make the output of PLLs in differrent FPGA devices synchronous with each oth
PLLs in differrent devices have the same settings and the same clock source(as attached plot). I need the PLL output of clk1 and clk2 to be synchronous with each other. How to do it? Could you help ...
Altera_ForumHonored Contributor
Honored ContributorJitter can't be expected to be basically lower in a source synchronous design than with an external clock, I think. But delay variations (skew) may actually reduce the sampling window down to or even below zero for a 250 MHz clock.
A defined clock phase relation can be desirable also for a source synchronous design.
