How to make the output of PLLs in differrent FPGA devices synchronous with each oth

I would like to ask the question, where there is the reason to do so?

The design method of synching two devices from the outside , lead me to the conclusion, that there ist the intention to transport data from one device to the other in one clock.

This hardly will work due to jitter. One should better perform synching on the data speed level or use frame synching methods within the system.