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Altera_Forum
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17 years ago

How to make the output of PLLs in differrent FPGA devices synchronous with each oth

PLLs in differrent devices have the same settings and the same clock source(as attached plot). I need the PLL output of clk1 and clk2 to be synchronous with each other. How to do it? Could you help ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Basically, a clock that is a multiple of inclock has a defined and reproducable phase by design. Deviations are expectable only from delay skew, but I can't see how to reduce them further by any means beyond the initially achieved synchronity.