Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to make the output of PLLs in differrent FPGA devices synchronous with each oth
PLLs in differrent devices have the same settings and the same clock source(as attached plot). I need the PLL output of clk1 and clk2 to be synchronous with each other. How to do it? Could you help ...
Altera_ForumHonored Contributor
Honored ContributorI doubt you will be able to achieve that goal.
At 250 MHz, the period is only 4 ns. The worst case difference is only +-2 ns How tight are you looking to get them?
