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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

How to make a custom IP (that integrated with an example design) to create testbench in Arria 10

Hi, I have a custom IP of a counter and that connected to the PCIe DMA transfer example design for the Arria 10 device(I have attached the counter code counter.v with this message). I also added ...
  • sstrell's avatar
    sstrell
    2 years ago

    No, the file you put in the simulation files section is the design file that should be used when the design is simulated, not a simulation testbench. This can be the same file as the synthesis file or it could be a different design file optimized for simulation.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

I don't know if the design optimization user guide goes into optimizing a design file for simulation. It probably focuses on optimizing for synthesis.

You'd probably want to check with your simulation tool vendor about optimizing for simulation. Using an optimized design for simulation can speed up the simulation process. Obviously, the best would be to use the same design file for both synthesis and simulation.

I was asking about all the component editor settings just to see if there were any other issues.