Forum Discussion
Altera_Forum
Honored Contributor
10 years agoHello all,
Coming from here (http://www.alteraforum.com/forum/showthread.php?t=48691) I'm trying to edit this into my verilog project.. I have built the HPS system, and found, the verilog files. From the verilog file I found three things could be done in the middle, but I don't understand how to get this right.. Do I need to call the hps_0 in my toplevel file? Or is it sufficient to declare the inputs and use them myself? (since the generated verilog file has the input declarations declared, and then calls the HPS_0) The "hps_io_hps_io_gpio_inst_LOANIO 01..x" do they need to be connected to the pins, (and declared in the QSF pin planning) despite that they are connected to the hardprocessor? Does the QIP file do anything to configure anything? Checking in after hrs, Will delve into this again tomorrow (Maybe find the golden formula), but if anyone knows and could save me and future readers some compiler time, Id be very thankfull.