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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

How to initiate a PCIe MSI/MSI-X interrupt ?

Hi : I use stratix10 series FPGA and PCIe AVMM DMA IP core，the system of the host computer is Linux，if I want to use multiple interrupts and software have different functions executed based on...
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VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi @allen18,


The software/driver implementation is out of my area of expertise, I’m happy to assist with any hardware-related aspects of the question.


There are two types of interrupts: legacy interrupt, and MSI and MSI-X interrupt.


MSI Interrupt:

Yes, MSI interrupt can be performed via the TXS interface. To trigger MSI interrupt, the Application can perform single DWORD memory writes, to be created by one of the AVMM slave interfaces. The Application can cause an MSI to be sent by the non-bursting Avalon-MM TX slave by performing a memory write to the non-bursting Avalon-MM TX slave. After the host receives an MSI it can service the interrupt based on the application defined interrupt service routine.


Besides, as many as 16 individual input interrupt signals are available but not 32 interrupt signals. You may find the rxm_irq_i [<m>:0], where <m> < 16 signal in Table 39 of the user guide given.

a. These signals connect interrupts to the AVMM interface. They are only available for the AVMM when the CRA port is enabled.

b. MSI interrupt is rising edge triggered. The hard IP core converts this event to an MSI interrupt and sends it to the Root Port.

c. The host reads the Interrupt Status register to retrieve the interrupt vector.

d. Host software services the interrupt and notifies the target upon completion.

e. The software must ensure that all interrupt sources are cleared for each MSI message received.

f. Note that, these signals are not available when the IP core is operating in DMA mode (i.e. when the Enable AVMM DMA option in the Avalon-MM Settings tab of the GUI is set to On)


The above findings are based on the below user guide: https://www.intel.com/content/www/us/en/docs/programmable/683667/23-1/introduction.html


You may also visit this article to learn more about the PCIe interrupts: https://community.intel.com/t5/FPGA-Wiki/Handling-PCIe-Interrupts/ta-p/736032


I hope these address your questions well.


Thanks.

Best Regards,

VenTing_Intel


p/s: If any answers from the community or Intel support are helpful, please feel free to mark them as solutions, give them kudos, and rate the survey 4/5.