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Honored Contributor
Honored ContributorHow to indicate a clk signal is differential in a MAX 10 FPGA
Hello, I am programming a MAX 10 FPGA and I would like to know how I can tell the device that the clk_in signal I defined in the top module is a differential clock. When compiling the project ...
Altera_ForumHonored Contributor
Honored ContributorI set it to a CLK_p pin that has an associated CLK_n pin but that did not generate any differential pair. I just tried what you suggested (I set my clk_in signal to a DIFF_p pin) and I got an error:
Error (176554): Can't place PLL "LVDS:I_LVDS|LVDS_0002:lvds_inst|lvds_rx_pll" -- I/O pin clk_in (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device The clock is not differential in my top-level list and how to define it as differential was actually one of my questions because that might solve the problem. As I said I defined an additional input to use both as differential inputs for a GOPIO Lite IP module and it did not work 100% (a differential pair was automatically generated but the additional input I defined was unasigned so I had an extra signal that I did not really need).
