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Altera_Forum
Honored Contributor
17 years agohow to increase frequency
Hi, I have written a code in Verilog and its frequency is comming out to be 28MHz only for Cyclone EPC6Q240C8 device. The place where frequency drops is Average Calculation. I have 3 regi...
Altera_Forum
Honored Contributor
17 years ago --- Quote Start --- truncating 3 bits(instead of explicit division): for 8 values average you need to divide the sum by 8 i.e. 2^3 so all you have to do is discard the 3 LSBs from sum4. using mult instead of divide(since dividers can be slower than multipliers): to divide by 9, final sum = sum4/9 = sum4 * 57/512 i.e. multiply sum4 by 57 then discard 9 bits off final result. The value 57 is derived from 512/9 you can and should use more bits for more accuracy: final sum = sum4 * 3641/32768 then discard 15 bits --- Quote End --- //------------------------------------------------------------ hey thanx everyone ...... the multiplication funda worked for me ....... multiplying the sum by 57 and then discarding the lsb 9 bits, frequency almost increased to 3 times ...... the design is now at 80MHz. cheers -amit garg