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Honored Contributor
Honored Contributorhow to increase frequency
Hi, I have written a code in Verilog and its frequency is comming out to be 28MHz only for Cyclone EPC6Q240C8 device. The place where frequency drops is Average Calculation. I have 3 regi...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- my longest path comming out to be is between sum4[8] and average[0]. and guys there is a typo error in my first post. my device is Cyclone EP1C6Q240C8. kaz - can u plz elaborate on the method of using 8 taps and then truncating 3 bits. GPK - what changes did you implement? Thank you --- Quote End --- Hi, I mainly switched on the "Physical Synthesis" Option, which allows Quartus to move Registers in your design, without changing the functionality. I have my Testproject attached to my last post. Have look at it. Kind regards GPK
