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Altera_Forum
Honored Contributor
17 years agohow to increase frequency
Hi, I have written a code in Verilog and its frequency is comming out to be 28MHz only for Cyclone EPC6Q240C8 device. The place where frequency drops is Average Calculation. I have 3 regi...
Altera_Forum
Honored Contributor
17 years ago --- Quote Start --- In that case, avoid division by either: Use 8 taps then just truncate 3 bits or use multiplier instead of division But in all cases I will pipeline all adders --- Quote End --- Hi Gargamit, I run test with your design. With Physcical Synhtesis I could improve your clock speed from 34 MHz to 66 MHz. I have the project attached. Kind regards GPK