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Altera_Forum
Honored Contributor
17 years agohow to increase frequency
Hi, I have written a code in Verilog and its frequency is comming out to be 28MHz only for Cyclone EPC6Q240C8 device. The place where frequency drops is Average Calculation. I have 3 regi...
Altera_Forum
Honored Contributor
17 years agoHi all,
I don't see the design is completely pipelined. all statements involving three additions can be further pipelined e.g. sum1 <= row1_reg[23:16] + row1_reg[15:8] + row1_reg[7:0]; into : sum1a <= row1_reg[23:16] + row1_reg[15:8]; sum1b <= row1_reg[7:0]; sum1 <= sum1a + sum1b; and so on. Moreover, there is another way of doing the average FIR filter using feedback and subtractor instead of full additions.