how to increase frequency

So the design is already completely pipelined. The /9 divider should be suspected as the slowest part. But it's likely to achieve more than 28 MHz to my opinion, unless you're stuck to a very slow device family. There must be something else, not understandable from the shown part, e. g. additional timing constraints related to the in and output signals. As pletz suggested, you have to examine the timing analysis details.