How to implement this logic in one Marocell?

The above logic circuit is inadequate in several respects:

- a LCELL implements logic operations by a LUT. The delay doesn't depend on the inplemented logic function. So it's meaningless to chain multiple logic symbols.

- in combinational mode, the register is bypassed

There have been various post dedicated to the topic of logic cell delay, e.g. http://www.alteraforum.com/forum/showthread.php?t=3068

The design compiler is required to remove all redundant logic cells in regular operation, so synthesis attributes must be used to tell him that you want to keep certain logic cells. The delay achievable by logic elements depends on involved device family, process parameters, temperature. With Cyclone III, I found a typical delay of 0.2 to 0.25 ns.

P.S.: I assume, that you refer to FPGA or FPGA-like MAX II. CPLDs are handled by a different synthesis tool, that apparently doesn't support the "keep" synthesis attribute.