how to implement 1M * 32 bits counters on EP4SGX230?

I once used some 600 counters(16 bits each) that required 600*16 = 9600 registers. Still too many. Then I managed to replace that with ram based 600 counters by updating a specific location by the new value computed by few shared adders. So you can share 1M counters on fewer adders depending on available speed. But the storage for 1M x 32 bit is too much for an FPGA and I think an external SDRAM will do.