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Bumjun
New Contributor
New ContributorHow to get high time resolution by operating a FPGA?
Hello. I would like to operate time-to-digital converter in FPGA.
My main question is how much time resolution can be taken in a FPGA?
There are two sub-questions.
One is that I see a specifi...
Ash_R_Altera
Regular Contributor
Regular ContributorHi,
Arria 10 I/O PLL can generate a max of 644 MHz for internal clocking (fOUT). I guess you might be mistaking the fVCO number of 1600MHz. Please refer the datasheet.
For the MAX 10 device you can create clocks (5 clocks) with a phase shift of 45 deg. Please refer following link for more information:
Regards
