How to get high time resolution by operating a FPGA?

Hi,

Arria 10 I/O PLL can generate a max of 644 MHz for internal clocking (fOUT). I guess you might be mistaking the fVCO number of 1600MHz. Please refer the datasheet.

For the MAX 10 device you can create clocks (5 clocks) with a phase shift of 45 deg. Please refer following link for more information:

https://www.intel.com/content/www/us/en/programmable/documentation/mcn1395213337540.html#mcn1395814790551

Regards