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we don't play magic Josyb. the given data clocking scheme is an implementation issue. You are referring back to possibilty 2 when data is clocked by 45MHz physical clock which is separate from 100Mhz and so needs crossing.
When you process your given fpga data(say from LUT) on 100Mhz with clken at 45Mhz then this fits possibilty 1. Thus data is already in 100Mhz domain and does not need any crossing but will need upsampling if it has to get rid of that clken rate of 45 and join the 100Mhz rate nicely.
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My point was that any
real data sampled at a different then system clock needs crossing.
What you referred to as 1) only exists when you downsample to a lower rate and back up again, hence my notion of a 'virtual' (or better said hypothetical?) clock.
I believe we have to stop here at some point, because we start saying the same thing with other words ...
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