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The original post is just saying a system clock is 100MHz, fpga modules need 45MHz clock. There is nothing about the issue of DAC or upsampling.
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I meant where we went off-topic ...
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With regard to upsampling diversion:
if you are given data at 45Mhz sampling rate then you will be told whether system clock is 45MHz or 100MHz (i.e. whether sampling rate = clock or is less).
1) possibility 1: data on 100MHz clock. If you want to upsample it to 100Mhz rate then you use an interpolation technique to create new samples.
2)possibility 2: data on 45MHz clock then you cross it over to 100MHz using dcfifo idea then interpolate it to 100MHz
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Say the system clock is 100 MHz and the data is sampled at 45 MHz, but magically is presented in the 100 MHz clock domain as you present in 1). How do we get the sampled data into that 100 MHz domain? I'd say we have to cross over somewhere.
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