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Altera_Forum
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16 years ago

How to generate a pulse smaller then cycle time

Hi Every body, i am a new user of FPGA and i am suffering from a basic problem, any one can help please :confused: i am using 16 MHz clock pulse of PCI for my FPGA, it corresponds to cycle time o...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Like any FPGA design, how fast will it run will depend on your target FPGA, it's speed grade, your design and the I/O standard you'll be using.

As a ball park number, 10 ns (100 MHz) is generally possible.