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Honored Contributor
Honored ContributorHow to generate a pulse smaller then cycle time
Hi Every body, i am a new user of FPGA and i am suffering from a basic problem, any one can help please :confused: i am using 16 MHz clock pulse of PCI for my FPGA, it corresponds to cycle time o...
Altera_ForumHonored Contributor
Honored Contributorthx for your help dear. how small pulse width can i generate using a PLL
