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DKron4
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7 years ago

How to generate 128-bit DDR3 interface on Cyclone 10 GX

I'm trying to implment a 128-bit DDR3 interface in a Cylone 10 GX 10CX105. I have made a design to test this, but cannot get successful placement. Is there a reference example of how to configure suc...
DKron4's avatar
DKron4
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7 years ago

Apologies, I realized I posted this to the wrong board. I reposted it to FPGA Intellectual Property, but I get an error while trying to delete this post.